Most electrical devices today, which may be boards, ICs or embedded cores within ICs, use the IEEE 1149.1 standard TAP and interface (referred to hereafter as JTAG TAP interface) to perform a variety of necessary operations, including but not limited to hardware test operations, hardware diagnostic operations, hardware/software debug operations, software trace operations and hardware programming operations. A number of additional IEEE standards have been created that also utilized the JTAG TAP interface to perform standardized operations beyond what the original JTAG TAP standard was designed to perform. Some of these additional IEEE standards include 1149.4, 1149.6, 1149.7, 1532, 1581, 1687, and 1500. The JTAG TAP interface of a device includes a test data input (TDI) terminal, a test clock (TCK) terminal, a test mode select (TMS) terminal, a test data output (TDO) terminal, and optionally a test reset (TRST) terminal. These device TAP interface terminals are dedicated and thus are available for enabling the above mentioned device operations at any point in the devices lifetime, i.e. device manufacturing through device system application.
FIG. 1 illustrates the standard JTAG TAP 100 within a device. The TAP 100 includes a TAP state machine (TSM) 102, an instruction register 104, data registers 106, TDO multiplexing circuitry 108, TDO output FF 110 and TDO output buffer 112. The TSM 102 has inputs coupled to the TMS 118 and TCK 120 device terminals and control outputs coupled to the other circuits within the TAP. The TRST input of TSM 102 may be coupled to a TRST device terminal 124 or to an internal power on reset circuit (POR) 114. The instruction register 104 and data registers 106 have inputs coupled to the TDI 116 device terminal and have serial outputs coupled to multiplexer 108. FF 110 has an input coupled to the output of multiplexer 108 and an output coupled to output buffer 112. When enabled, buffer 112 outputs data to the TDO device terminal 122.
The TMS, TCK and optional TRST terminals, are connected to the JTAG controller. The TDI terminal may be connected to the JTAG controller or to the TDO terminal of a leading device TAP in a series arrangement. The TDO terminal may be connected to the JTAG controller or to the TDI terminal of a trailing device TAP in a series arrangement. The TSM 102 responds to TMS and TCK according to the TAP state diagram of FIG. 3 to; (1) enter a Test Logic Reset state 302, (2) enter a Run Test/Idle state 304, (3) to perform a data register scan operation 306 from TDI to TDO, or (4) to perform an instruction scan operation 308 from TDI to TDO.
FIG. 2 illustrates a timing example of the TCK, TMS, TDI and TDO signals according to the IEEE 1149.1 standard. As seen, TMS, TDI and TDO signals transition on the falling edge of TCK and are sampled on the rising edge of TCK. The structure and operation of the TAP, its state diagram, and timing of its TDI, TCK, TMS and TDO signals are well known in the industry.
As seen in FIGS. 4-6, a JTAG TAP controller may be coupled to the TAP 100 terminals of a single device (FIG. 4), to the TAP 100 terminals of a group of parallel arranged devices (FIG. 5), or to the TAP 100 terminals of a group of serially arranged devices (FIG. 6). In FIG. 5, a connection between a JTAG controller and the TAP terminals of a group of parallel arranged devices requires the JTAG controller to have a dedicated TMS signal for each of the parallel devices, so that each device TAP 100 can be separately accessed. For example, if 20 parallel devices are connected to a controller, the controller would have to have 20 TMS 118 signals, in addition to the TDI 116, TCK 120, and TDO 122 signals.
The parallel arrangement of FIG. 5 is preferred over the serial arrangement of FIG. 6 in a number of situations. One situation is when the TAPs of devices 1-N have different maximum TCK operation rates. For example, device 1 may have a maximum TCK rate of 10 Mhz while device N has a maximum TCK rate of 100 Mhz. If devices 1 and N were serially arranged as shown in FIG. 6, the 100 Mhz TCK operation rate of device N could never be exploited since the 10 Mhz maximum TCK operation rate of device 1 would set the speed at which the serially arranged device TAPs operate. If devices 1 and N were parallel arranged as shown in FIG. 5, each device could be accessed separately and at it maximum TCK rate. Being able to access a device's TAP at is maximum TCK is essential for decreasing the time it takes to execute device operations such as, but not limited to, test, debug, trace, and programming operations.
Another situation where the parallel arrangement of FIG. 5 is preferred over the serial arrangement of FIG. 6 is when reliable access to a device TAP is required. For example, in FIG. 6, since all device TAPs are in series, a failure in one device TAP would disable access to all other device TAPs. However in FIG. 5 the access to a device TAP is not dependent upon the operation of another device TAP. So the parallel arrangement of FIG. 5 is more tolerant to faults than the serial arrangement of FIG. 6.
While the parallel TAP arrangement of FIG. 5 is advantageous in the above mentioned situations, the increase in interface wiring (TMS signals 1-N) between the controller and parallel devices is problematic in applications where the number of JTAG signal connections must be limited to only the required TDI, TCK, TMS and TDO signals. As will be described in detail below, the disclosure advantageously provides a method and apparatus for enabling a JTAG controller to access parallel arranged device TAPs to achieve the benefits mentioned above using only the required TDI, TCK, TMS and TDO JTAG signal bus.